cracauer@
Developer
BTW, it is getting even more complicated.
Intel is introducing E-cores that are outside the CCD and are not connected to the L3 cache. The purpose is to be able to power down the entire CCD with the P-cores and normally connected E-cores while keeping the computer alive on a slow cooker. The E-cores on and off the main CCD are otherwise identical, except for cache access.
Good luck making scheduler decisions for that one.
Intel is introducing E-cores that are outside the CCD and are not connected to the L3 cache. The purpose is to be able to power down the entire CCD with the P-cores and normally connected E-cores while keeping the computer alive on a slow cooker. The E-cores on and off the main CCD are otherwise identical, except for cache access.
Good luck making scheduler decisions for that one.