no, but you can use a vm inside a supported osThanks, does FreeBSD support it?
still performance will rock compared with other boards
no, but you can use a vm inside a supported osThanks, does FreeBSD support it?
That crossed my mind ...
But I don't want that - I want to run FreeBSD on the bare metal...
Hi tingo, me too. But I am considering that. If i find a good buying option on that Oragne pi 6 plus I will really consider. Now I am looking for the ethernet chip to see if its compatible, and for firmware options (u-boot and edk2, so far nothing found - had not much time on that though). The Orange Pi 5 Plus is an option as well, but also not supported. OpenBSD supports it with everything working, so I may try running VM's on it, as its closer to FreeBSD then Linux. I don't dislike Linux, I just like BSD* better, way better.But I don't want that - I want to run FreeBSD on the bare metal...
github.com
marietto# pwd
/mnt/zroot2/zroot2/OS/BSD/FreeBSD/arm64/socs/Radxa-3W/Stuff/drm-subtree
marietto# find . -name "*.ko"
./modules/panfrost/panfrost.ko
./modules/drm_kmod/drm_kmod.ko
./modules/rockchip/rk_drm/rk_drm.ko
./modules/rockchip/rk_vop2/rk_vop2.ko
./modules/rockchip/rk_dw_hdmi/rk_dw_hdmi.koThis don't sound right to me.
git clone -b releng/15.0 https://git.freebsd.org/src.git /usr/srcdiff --git a/sys/dev/sdhci/sdhci_fdt_rockchip.c b/sys/dev/sdhci/sdhci_fdt_rockchip.c
index 44a5e2ffe271..b6b916bbb40a 100644
--- a/sys/dev/sdhci/sdhci_fdt_rockchip.c
+++ b/sys/dev/sdhci/sdhci_fdt_rockchip.c
@@ -74,14 +74,17 @@
#define RK3399_GRF_EMMCCORE_CON11 0xf02c
#define RK3399_CORECFG_CLOCKMULTIPLIER 0xff
+#define RK35XX_CTRL_HS400 0x7
#define RK3568_EMMC_HOST_CTRL 0x0508
#define RK3568_EMMC_EMMC_CTRL 0x052c
+#define RK35XX_CARD_IS_EMMC 0x1
#define RK3568_EMMC_ATCTRL 0x0540
#define RK3568_EMMC_DLL_CTRL 0x0800
#define DLL_CTRL_SRST 0x00000001
#define DLL_CTRL_START 0x00000002
#define DLL_CTRL_START_POINT_DEFAULT 0x00050000
#define DLL_CTRL_INCREMENT_DEFAULT 0x00000200
+#define DLL_CTRL_BYPASS 0x01000000
#define RK3568_EMMC_DLL_RXCLK 0x0804
#define DLL_RXCLK_DELAY_ENABLE 0x08000000
@@ -95,7 +98,12 @@
#define RK3568_EMMC_DLL_STRBIN 0x080c
#define DLL_STRBIN_DELAY_ENABLE 0x08000000
#define DLL_STRBIN_TAPNUM_DEFAULT 0x00000008
-#define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000
+#define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000
+#define DLL_STRBIN_DELAY_NUM_SEL 0x04000000
+#define DLL_STRBIN_DELAY_NUM_OFFSET 0x10
+#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
+
+#define RK3568_EMMC_DLL_CMDOUT 0x0810
#define RK3568_EMMC_DLL_STATUS0 0x0840
#define DLL_STATUS0_DLL_LOCK 0x00000100
@@ -164,67 +172,82 @@ static int
sdhci_fdt_rockchip_set_clock(device_t dev, struct sdhci_slot *slot, int clock)
{
struct sdhci_fdt_softc *sc = device_get_softc(dev);
+ uint32_t uval;
int32_t val;
int i;
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
SDHCI_FDT_RK3568) {
- if (clock == 400000)
- clock = 375000;
-
- if (clock) {
- clk_set_freq(sc->clk_core, clock, 0);
-
- if (clock <= 52000000) {
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_CTRL, 0x0);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_NO_INV);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_TXCLK, 0x0);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_STRBIN, 0x0);
- return (clock);
- }
-
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_CTRL, DLL_CTRL_START);
- DELAY(1000);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_CTRL, 0);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_CTRL, DLL_CTRL_START_POINT_DEFAULT |
- DLL_CTRL_INCREMENT_DEFAULT | DLL_CTRL_START);
- for (i = 0; i < 500; i++) {
- val = bus_read_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_STATUS0);
- if (val & DLL_STATUS0_DLL_LOCK &&
- !(val & DLL_STATUS0_DLL_TIMEOUT))
- break;
- DELAY(1000);
- }
- bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL,
- (0x1 << 16 | 0x2 << 17 | 0x3 << 19));
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_RXCLK,
- DLL_RXCLK_DELAY_ENABLE | DLL_RXCLK_NO_INV);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_TXCLK, DLL_TXCLK_DELAY_ENABLE |
- DLL_TXCLK_TAPNUM_DEFAULT|DLL_TXCLK_TAPNUM_FROM_SW);
- bus_write_4(sc->mem_res[slot->num],
- RK3568_EMMC_DLL_STRBIN, DLL_STRBIN_DELAY_ENABLE |
- DLL_STRBIN_TAPNUM_DEFAULT |
- DLL_STRBIN_TAPNUM_FROM_SW);
- }
- }
- return (sdhci_fdt_set_clock(dev, slot, clock));
+ if (clock == 400000)
+ clock = 375000;
+ if (clock) {
+ clk_set_freq(sc->clk_core, clock, 0);
+ uval = bus_read_4(sc->mem_res[slot->num],
+ RK3568_EMMC_HOST_CTRL) & (~1);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_HOST_CTRL, uval);
+
+ if (clock <= 52000000) {
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_CTRL,
+ DLL_CTRL_START | DLL_CTRL_BYPASS);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_NO_INV);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_TXCLK, 0x0);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_CMDOUT, 0x0);
+
+ uval = DLL_STRBIN_DELAY_ENABLE |
+ DLL_STRBIN_DELAY_NUM_SEL |
+ DLL_STRBIN_DELAY_NUM_DEFAULT <<
+ DLL_STRBIN_DELAY_NUM_OFFSET;
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_STRBIN, uval);
+ return (clock);
+ }
+
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_CTRL, DLL_CTRL_START);
+ DELAY(1000);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_CTRL, 0);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_CTRL, DLL_CTRL_START_POINT_DEFAULT |
+ DLL_CTRL_INCREMENT_DEFAULT | DLL_CTRL_START);
+ for (i = 0; i < 500; i++) {
+ val = bus_read_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_STATUS0);
+ if (val & DLL_STATUS0_DLL_LOCK &&
+ !(val & DLL_STATUS0_DLL_TIMEOUT))
+ break;
+ DELAY(1000);
+ }
+ bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL,
+ (0x1 << 16 | 0x3 << 17 | 0x3 << 19));
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_RXCLK,
+ DLL_RXCLK_DELAY_ENABLE | DLL_RXCLK_NO_INV);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_TXCLK, DLL_TXCLK_DELAY_ENABLE |
+ DLL_TXCLK_TAPNUM_DEFAULT | DLL_TXCLK_TAPNUM_FROM_SW|
+ DLL_RXCLK_NO_INV);
+ bus_write_4(sc->mem_res[slot->num],
+ RK3568_EMMC_DLL_STRBIN, DLL_STRBIN_DELAY_ENABLE |
+ DLL_STRBIN_TAPNUM_DEFAULT |
+ DLL_STRBIN_TAPNUM_FROM_SW);
+ }
+ }
+ return (clock);
+
}
static int
sdhci_fdt_rockchip_attach(device_t dev)
{
struct sdhci_fdt_softc *sc = device_get_softc(dev);
- int err, compat;
+ int i, err, compat;
+ char *rk35xx_clocks[] = {"bus", "timer", "axi", "block" };
sc->dev = dev;
compat = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
@@ -257,6 +280,19 @@ sdhci_fdt_rockchip_attach(device_t dev)
return (ENXIO);
}
clk_enable(sc->clk_core);
+
+ for (i = 0; i < nitems(rk35xx_clocks);i++) {
+ clk_t clk_tmp;
+
+ if (clk_get_by_ofw_name(dev, 0,rk35xx_clocks[i], &clk_tmp)) {
+ device_printf(dev, "cannot get %s clock\n",
+ rk35xx_clocks[i]);
+ return (ENXIO);
+ }
+ err = clk_enable(clk_tmp);
+ if (err)
+ break;
+ }
break;
default:
break;diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi
index 93189f830640..e7df980d2c74 100644
--- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi
+++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi
@@ -146,18 +146,22 @@
&cpu0 {
cpu-supply = <&vdd_cpu>;
+ clocks = <&cru ARMCLK>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
+ clocks = <&cru ARMCLK>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
+ clocks = <&cru ARMCLK>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
+ clocks = <&cru ARMCLK>;
};
&gpu {
@@ -232,6 +236,7 @@
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
+ regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
@@ -245,6 +250,7 @@
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
+ regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
@@ -268,6 +274,7 @@
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
@@ -470,6 +477,7 @@
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
@@ -487,6 +495,7 @@
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
+ disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
status = "okay";/dev/mmcsd0p4 / ufs rw,noatime 1 1
#/dev/gpt/efi /boot/firmware msdosfs rw,noatime 0 0
md /tmp mfs rw,noatime,-s64m 0 0
md /var/log mfs rw,noatime,-s32m 0 0
md /var/tmp mfs rw,noatime,-s8m 0 0/dev/mmcsd0p4 / ufs rw,noatime 1 1ufs:/dev/mmcsd0p4Sounds really nice, is it the rk3399,iommu or what is the compat? Can you share the code?
well the window / plane is being disabled before the iommu unmap happens but somehow the vop still tries to read from it and faults
I am trying to incorporate your iommu in the rk3399 vop and plane..
/* rockchip iommus are 0 cells */
if (OF_hasprop(sc->node, "iommus")) {
error = ofw_bus_parse_xref_list_alloc(sc->node, "iommus", "#iommu-cells",
0, &iommu_parent, &ncells, &cells);
if (error != 0) {
device_printf(dev, "%s can't get iommu device xref.\n",
__func__);
}
sc->iommu_dev = OF_device_from_xref(iommu_parent);
} paddr = bo->pbase + fb->drm_fb.offsets[0];
paddr += (state->src.x1 >> 16) * fb->drm_fb.format->cpp[0];
paddr += (state->src.y1 >> 16) * fb->drm_fb.pitches[0];
if (id == 0)
VOP_WRITE(sc, RK3399_WIN0_YRGB_MST, paddr);
else
VOP_WRITE(sc, RK3399_WIN2_MST0, paddr);static void vop2_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *jstate)
{
....
struct drm_plane_state *pstate = plane->state;
....
struct drm_framebuffer *fb = pstate->fb;
struct rk_gem_object *bo;
struct rk_fb *rkfb;
....
rkfb = (struct rk_fb *) fb;
bo = (struct rk_gem_object *)(rkfb->planes[0]);