cmpxchg16b instruction

gtroxler · Mar 7, 2010

When compiling code, that contains the following inline asm instruction "cmpxchg16b" I receive the following error:

Code:

: Assembler messages:
: Error: no such instruction: `cmpxchg16b (%rdi)'

Does anybody have a clue for this behavior?

gcc is version 4.4.2 20090915 (prerelease) (GCC). The -mcx16 flag does not help.

Code:

uname -a
FreeBSD dev0zh_bsd     8.0-RELEASE FreeBSD 8.0-RELEASE #0: Sat Nov 21 15:02:08 UTC 2009
     root@mason.cse.buffalo.edu:/usr/obj/usr/src/sys/GENERIC  amd64

cpuid shows:

Code:

 eax in    eax      ebx      ecx      edx
00000000 0000000a 756e6547 6c65746e 49656e69 
00000001 00010676 04040800 000ce3bd bfebfbff 
00000002 05b0b101 005657f0 00000000 2cb4304e 
00000003 00000000 00000000 00000000 00000000 
00000004 0c000121 01c0003f 0000003f 00000001 
00000005 00000040 00000040 00000003 00002220 
00000006 00000001 00000002 00000001 00000000 
00000007 00000000 00000000 00000000 00000000 
00000008 00000400 00000000 00000000 00000000 
00000009 00000000 00000000 00000000 00000000 
0000000a 07280202 00000000 00000000 00000503 
80000000 80000008 00000000 00000000 00000000 
80000001 00000000 00000000 00000001 20100800 
80000002 65746e49 2952286c 6f655820 2952286e 
80000003 55504320 20202020 20202020 45202020 
80000004 32363435 20402020 30382e32 007a4847 
80000005 00000000 00000000 00000000 00000000 
80000006 00000000 00000000 18008040 00000000 
80000007 00000000 00000000 00000000 00000000 
80000008 00003026 00000000 00000000 00000000 

Vendor ID: "GenuineIntel"; CPUID level 10

Intel-specific functions:
Version 00010676:        
Type 0 - Original OEM    
Family 6 - Pentium Pro   
Model 7 - Pentium III/Pentium III Xeon - external L2 cache
Stepping 6                                                
Reserved 4                                                

Extended brand string: "Intel(R) Xeon(R) CPU           E5462  @ 2.80GHz"
CLFLUSH instruction cache line size: 8                                  
Initial APIC ID: 4                                                      
Hyper threading siblings: 4                                             

Feature flags: bfebfbff:
FPU    Floating Point Unit
VME    Virtual 8086 Mode Enhancements
DE     Debugging Extensions          
PSE    Page Size Extensions          
TSC    Time Stamp Counter            
MSR    Model Specific Registers      
PAE    Physical Address Extension    
MCE    Machine Check Exception       
CX8    COMPXCHG8B Instruction        
APIC   On-chip Advanced Programmable Interrupt Controller present and enabled
SEP    Fast System Call                                                      
MTRR   Memory Type Range Registers                                           
PGE    PTE Global Flag                                                       
MCA    Machine Check Architecture                                            
CMOV   Conditional Move and Compare Instructions                             
FGPAT  Page Attribute Table                                                  
PSE-36 36-bit Page Size Extension                                            
CLFSH  CFLUSH instruction                                                    
DS     Debug store                                                           
ACPI   Thermal Monitor and Clock Ctrl                                        
MMX    MMX instruction set
FXSR   Fast FP/MMX Streaming SIMD Extensions save/restore
SSE    Streaming SIMD Extensions instruction set
SSE2   SSE2 extensions
SS     Self Snoop
HT     Hyper Threading
TM     Thermal monitor
31     reserved

Feature flags set 2: 000ce3bd:
SSE3     SSE3 extensions
DTES64   64-bit debug store
MONITOR  MONITOR/MWAIT instructions
DS-CPL   CPL Qualified Debug Store
VMX      Virtual Machine Extensions
EST      Enhanced Intel SpeedStep Technology
TM2      Thermal Monitor 2
SSSE3    Supplemental Streaming SIMD Extension 3
CX16     CMPXCHG16B
xTPR     Send Task Priority messages
PDCM     Perfmon and debug capability
DCA      Direct Cache Access
SSE4.1   Streaming SIMD Extension 4.1

Extended feature flags: 20100800:
SYSCALL   SYSCALL/SYSRET instructions
XD-bit    Execution Disable bit
EM64T     Intel Extended Memory 64 Technology

Extended feature flags set 2: 00000001:
0 - unknown feature

TLB and cache info:
b1: Instruction TLB: 2MB Pages (8 entries) or 4MB pages (4 entries), 4-way set associative
b0: Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
05: Data TLB: 4MB pages, 4-way set assoc, 32 entries
f0: 64-byte prefetching
57: Data TLB: 4KB pages, 4-way set associative, 16 entries
56: Data TLB: 4MB pages, 4-way set associative, 16 entries
4e: 3rd-level cache: 6MB, 24-way set associative, 64-byte line size
30: 1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size
b4: Data TLB: 4-KB Pages, 4-way set associative, 256 entries
2c: 1st-level data cache: 32-KB, 8-way set associative, 64-byte line size
Processor serial: 0001-0676-0000-0000-0000-0000

graudeejs · Mar 7, 2010

assembler doesn't support it,
You know (and can calculate address) code, you can insert hex code directly (db 0x..., haven't been writing x86 asm code for years, so I don't remember exact syntax

) , this will be hackish workaround, for assembler

here's small tip about asm instruction hex

http://ref.x86asm.net/coder32.html

cmpxchg16b instruction

gtroxler

graudeejs