Sure. An algorithm can be implemented in a lot of ways, choosing a hardware description language and going for silicon is only one way to do it. As I was pointing out before, you need to get your mind around the parallel nature of hardware in order to create efficient and maintainable implementations. This kind of thinking is not widely seen, and it is not taught at universities to the masses. So there are not that many people who can do this. That is point number one. Point number two is that reconfigurable hardware is not really cheap.
FPGAs are more expensive per unit when compared with mass produced ASICs. Well, they are also ASICs, but you need more die area for the same amount of logic due to the reconfigurability and flexible routing resources, so they are simply more expensive per unit. So you, as a customer, would pay several times the money you would pay for, say, a Core-I3 for a chip that comes close in logical capacity (number of gates/transistors/...). And there is no software available off the shelf for it. But it can run circles around its counterpart for workloads which profit from a high level of parallel execution.
The sweet spot, economically, is the CPU as we know it. The hardware is not changable while running (okay, certain microcode patches would make it seem that way), the re-configuration is done by the software which tells the hardware how to switch states, one operation after the other. Not as fast as a custom tailored ASIC, not as flexible as an FPGA, but a lot less drain on the wallet.