Pi Zero format boards that are supported.


---> xrandr --prop| edid-decode (edid-decode is an external package)


Nope,this one is correct :

Code:
# edid-decode /sys/class/drm/card0-HDMI-A-1/edid
 
in ./edk2-rockchip/Silicon/Rockchip/Rk356x/Drivers/DisplayDxe/DwHdmi.c
Code:
     switch (PixelClock * 10) {
     case 594000:
     case 297000:
     case 148500:
     case 74250:
+    case 44000:
+    case 27000:
Diff:
     for (NumExt = 0; NumExt < MIN (MAX_EDID_EXTENSION_BLOCKS, Buf[126]); NumExt++) {
-        Status = DwHdmiEdidRead (1 + NumExt, &Buf[128 + (1 + NumExt)], 128);
+        Status = DwHdmiEdidRead (1 + NumExt, &Buf[128 * (1 + NumExt)], 128);
         if (Status != EFI_SUCCESS) {
             break;
         }
     }
add this mods and it should support edid detection; the board should work on boh the big and small display in their native resolution
 
in ./edk2-rockchip/Silicon/Rockchip/Rk356x/Drivers/DisplayDxe/DwHdmi.c
Code:
     switch (PixelClock * 10) {
     case 594000:
     case 297000:
     case 148500:
     case 74250:
+    case 44000:
+    case 27000:
Diff:
     for (NumExt = 0; NumExt < MIN (MAX_EDID_EXTENSION_BLOCKS, Buf[126]); NumExt++) {
-        Status = DwHdmiEdidRead (1 + NumExt, &Buf[128 + (1 + NumExt)], 128);
+        Status = DwHdmiEdidRead (1 + NumExt, &Buf[128 * (1 + NumExt)], 128);
         if (Status != EFI_SUCCESS) {
             break;
         }
     }
add this mods and it should support edid detection; the board should work on boh the big and small display in their native resolution

you should be more clear here. I don't understand if the previous changes should be applied or not.
 
the lines that begin with + should be added and the ones with '-' removed
do not add the '+' symbol, only the rest of the line
first is about line 140 and the other at 320
 
The changes below should be applied together with your last one,or the last one is enough and the changes that I have remembered below should be ignored ?

1) change the values here :

https://github.com/jaredmcneill/qua...ckchip/Rk356x/Drivers/DisplayDxe/DisplayDxe.c

with these ones :

/* Fallback to 720p when DDC fails */
STATIC HDMI_DISPLAY_TIMING mDefaultTimings = {
.Vic = 0,
.FrequencyKHz = 44000,
.HDisplay = 720, .HSyncStart = 820, .HSyncEnd = 900, .HTotal = 976, .HSyncPol = FALSE,
.VDisplay = 720, .VSyncStart = 738, .VSyncEnd = 742, .VTotal = 754, .VSyncPol = TRUE,
};

2)

in DwHdmi.c at DWHDMI_MPLL_CONFIG mDwHdmiMpllConfig[] = {

add this the second line

{ 46000, 0x00b3, 0x0000, 0x0000 },

between the { 40000... line and the { 65000 ....line

and rebuild

3)

in ./edk2-rockchip/Silicon/Rockchip/Rk356x/Library/CruLib/CruLib.c

at STATIC CRU_PLL_RATE CruPllRates[] = {

delete all the array definition and replace it with this :

STATIC CRU_PLL_RATE CruPllRates[] = {
{ .Rate = 2208000000U, .FbDiv = 92, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 2184000000U, .FbDiv = 91, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 2160000000U, .FbDiv = 90, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 2088000000U, .FbDiv = 87, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 2064000000U, .FbDiv = 86, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 2040000000U, .FbDiv = 85, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 2016000000U, .FbDiv = 84, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1992000000U, .FbDiv = 83, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1920000000U, .FbDiv = 80, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1896000000U, .FbDiv = 79, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1800000000U, .FbDiv = 75, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1704000000U, .FbDiv = 71, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1608000000U, .FbDiv = 67, .PostDiv1 = 1, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1600000000U, .FbDiv = 200, .PostDiv1 = 1, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1584000000U, .FbDiv = 132, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1560000000U, .FbDiv = 130, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1536000000U, .FbDiv = 128, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1512000000U, .FbDiv = 126, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1488000000U, .FbDiv = 124, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1464000000U, .FbDiv = 122, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1440000000U, .FbDiv = 120, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1416000000U, .FbDiv = 118, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1400000000U, .FbDiv = 350, .PostDiv1 = 2, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1392000000U, .FbDiv = 116, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1368000000U, .FbDiv = 114, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1344000000U, .FbDiv = 112, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1320000000U, .FbDiv = 110, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1296000000U, .FbDiv = 108, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1272000000U, .FbDiv = 106, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1248000000U, .FbDiv = 104, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1200000000U, .FbDiv = 100, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1188000000U, .FbDiv = 99, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1104000000U, .FbDiv = 92, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1100000000U, .FbDiv = 275, .PostDiv1 = 2, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1008000000U, .FbDiv = 84, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 1000000000U, .FbDiv = 250, .PostDiv1 = 2, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 912000000U, .FbDiv = 76, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 816000000U, .FbDiv = 68, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 800000000U, .FbDiv = 200, .PostDiv1 = 2, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 724000000U, .FbDiv = 181, .PostDiv1 = 2, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 700000000U, .FbDiv = 350, .PostDiv1 = 4, .RefDiv = 3, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 696000000U, .FbDiv = 116, .PostDiv1 = 4, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 600000000U, .FbDiv = 100, .PostDiv1 = 4, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 594000000U, .FbDiv = 99, .PostDiv1 = 4, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 500000000U, .FbDiv = 125, .PostDiv1 = 6, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 408000000U, .FbDiv = 68, .PostDiv1 = 2, .RefDiv = 1, .PostDiv2 = 2, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 312000000U, .FbDiv = 78, .PostDiv1 = 6, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 297000000U, .FbDiv = 99, .PostDiv1 = 4, .RefDiv = 2, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 292500000U, .FbDiv = 195, .PostDiv1 = 4, .RefDiv = 1, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 241500000U, .FbDiv = 161, .PostDiv1 = 4, .RefDiv = 2, .PostDiv2 = 2, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 216000000U, .FbDiv = 72, .PostDiv1 = 4, .RefDiv = 1, .PostDiv2 = 2, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 200000000U, .FbDiv = 100, .PostDiv1 = 3, .RefDiv = 1, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 148500000U, .FbDiv = 99, .PostDiv1 = 4, .RefDiv = 1, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 135000000U, .FbDiv = 45, .PostDiv1 = 4, .RefDiv = 2, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 128000000U, .FbDiv = 16, .PostDiv1 = 3, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 126400000U, .FbDiv = 79, .PostDiv1 = 5, .RefDiv = 1, .PostDiv2 = 3, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 119000000U, .FbDiv = 119, .PostDiv1 = 4, .RefDiv = 3, .PostDiv2 = 2, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 115200000U, .FbDiv = 24, .PostDiv1 = 5, .RefDiv = 1, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 108000000U, .FbDiv = 45, .PostDiv1 = 5, .RefDiv = 2, .PostDiv2 = 1, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 101000000U, .FbDiv = 101, .PostDiv1 = 6, .RefDiv = 1, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 100000000U, .FbDiv = 150, .PostDiv1 = 6, .RefDiv = 1, .PostDiv2 = 6, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 96000000U, .FbDiv = 96, .PostDiv1 = 6, .RefDiv = 1, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 78750000U, .FbDiv = 315, .PostDiv1 = 6, .RefDiv = 4, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 74250000U, .FbDiv = 99, .PostDiv1 = 4, .RefDiv = 2, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 44000000U, .FbDiv = 44, .PostDiv1 = 6, .RefDiv = 1, .PostDiv2 = 4, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 27000000U, .FbDiv = 45, .PostDiv1 = 5, .RefDiv = 4, .PostDiv2 = 2, .Dsmpd = 1, .Frac = 0, },
{ .Rate = 0 },
};
 
together with the previous ones
if it works after this last one with both screens then the one with the screen data can be reverted to original (ie fall back to 720p if edid fails). so the image will be usable on a more std screen that the 720x720
 
Have you checked the frequency of your cores? Check to see..
sysctl dev.cpu.0.freq
How does top look for memory usage? gstat your disk usage.
Find the bottleneck.
scfb driver setup?
 
Single video stream from u-tube should be possible on scfb. It works on x86.

Have you seen any progress on Rockchip DRM driver for FreeBSD? That should help. There are hardware features here.
 
One idea that is intriguing me is to use the version of Firefox bundled with the tor-browser package. I see that it is a little bit old,but fast. Not sure if I can use it without connecting to the tor network...
 
Well the article does mention RK3399. So for desktop features that is probably what you need.


I really have not heard of anybody using panfrost drivers on FreeBSD. Interesting.

I tried to install the panfrost driver on my RockPro RK3399 following the instructions found here :


So :

Code:
# git clone https://github.com/evadot/drm-subtree.git
Cloning into 'drm-subtree'...
remote: Enumerating objects: 2189, done.
remote: Counting objects: 100% (286/286), done.
remote: Compressing objects: 100% (57/57), done.
remote: Total 2189 (delta 252), reused 235 (delta 229), pack-reused 1903 (from 1)
Receiving objects: 100% (2189/2189), 1.49 MiB | 3.32 MiB/s, done.
Resolving deltas: 100% (1440/1440), done.
Updating files: 100% (445/445), done.

# cd drm-subtree/
# git checkout -b drm-base-subtree
Switched to a new branch 'drm-base-subtree'

# git remote add drm-subtree https://github.com/evadot/drm-subtree.git

# git subtree add --prefix sys/dev/drm/ drm-subtree master
git fetch drm-subtree master
From https://github.com/evadot/drm-subtree
 * branch            master     -> FETCH_HEAD
 * [new branch]      master     -> drm-subtree/master
Added dir 'sys/dev/drm'

# git am sys/dev/drm/extra_patches/*.patch
Applying: Hook DRM to the build
error: sys/conf/kern.pre.mk: does not exist in index
error: sys/conf/options: does not exist in index
Patch failed at 0001 Hook DRM to the build
hint: Use 'git am --show-current-patch=diff' to see the failed patch
hint: When you have resolved this problem, run "git am --continue".
hint: If you prefer to skip this patch, run "git am --skip" instead.
hint: To restore the original branch and stop patching, run "git am --abort".
hint: Disable this message with "git config set advice.mergeConflict false"
 
Patches from a four year old article could be troublesome.

You need to bounce patch against code and see if it is already committed.
 
So dig around newer source tree and look at
/usr/src/sys/dev/drm

There used to be a i915drm driver in base but it was pulled out and sent to ports. So I don't know if all DRM was removed or what. It helps to know history.

Start digging into source. It is not easy but needed. Research the code commitals for the /drm directory.
 
So dig around newer source tree and look at
/usr/src/sys/dev/drm

There used to be a i915drm driver in base but it was pulled out and sent to ports. So I don't know if all DRM was removed or what. It helps to know history.

Start digging into source. It is not easy but needed. Research the code commitals for the /drm directory.

Thanks. I know that you hate to read this,but I don't know where to start. This is too advanced for me.
 
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