Consider the following Makefile.
In an attempt to create a uniform file that works with both GNU and BSD, the attempt failed.
Ok let's stick with a purely BSD working solution. I want the Makefile to achieve two objectives:
1. Source and Object files are to be in different sub/directories
2. In addition to the default target I want to establish a second, debug target.
Writing everything out explicitly this is what I have:
It is still not entirely correct because
doesn't expand the inputs.
The expansion has the following template:
and
notion doesn't seem to work because files and targets are not in the same directory.
If I define the list
how can I get make to operate on each element of the list??
In an attempt to create a uniform file that works with both GNU and BSD, the attempt failed.
Ok let's stick with a purely BSD working solution. I want the Makefile to achieve two objectives:
1. Source and Object files are to be in different sub/directories
2. In addition to the default target I want to establish a second, debug target.
Writing everything out explicitly this is what I have:
Code:
OBJ=obj/dummy0.o obj/dummy1.o
OBJ_DBG=obj/dummy0~dbg.o obj/dummy1~dbg.o
all: dummy
dbg: dummy_dbg
dummy_dbg: $(OBJ_DBG)
@echo "Link with Debug..."
@echo $(OBJ_DBG) "-->" $@~dbg
obj/dummy0~dbg.o: src/dummy0.x
@echo Build Debug $< $@
obj/dummy1~dbg.o: src/dummy1.x
@echo Build Debug $< $@
dummy: $(OBJ)
@echo Link with Release...
@echo $(OBJ) "-->" $@
obj/dummy0.o: src/dummy0.x
@echo Build Release $< $@
obj/dummy1.o: src/dummy1.x
@echo Build Release $< $@
clean:
@echo Cleaning...
rm -f obj/*.o
It is still not entirely correct because
Code:
$<
The expansion has the following template:
Code:
all: dummy
dummy: $(OBJ)
$(OBJ): $(SRC)
@............
Code:
.SUFFIXES
Code:
.x.o
If I define the list
Code:
SRC