Z80 not dead - 50th Birthday Party!

blackbird9

blackbird9

hardware.slashdot.org

Zilog Z80 8-Bit CPU Turns 50, Open-source Replacement Heads To Drop-in DIP40 Silicon - Slashdot

An anonymous reader shared this report from Tom's Hardware: The Zilog Z80 has just turned 50 years old. This iconic 8-bit processor first went on sale in July 1976 and stayed in production for 48 years until Zilog, now a Littelfuse subsidiary, stopped accepting orders in June 2024. However...
hardware.slashdot.org

"Renaldas Zioma's FOSS Z80 project, launched shortly after the end-of-life notice, now has working silicon. The first version, fabbed on SkyWater's 130nm node through Tiny Tapeout 7 on a die of just 0.064mm(2), has been confirmed as functional via the project's GitHub repository. A QFN64 version with all 40 pins exposed followed on the Efabless CI2406 shuttle, two further runs then went through IHP's 130nm process, and the current run targets the classic DIP40 form factor using chip-on-board assembly on GlobalFoundries' 180nm GF180MCU node via Wafer.Space. The end goal here is to fab a drop-in replacement."

They have got to first silicon. This can only be good news. 😁

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We need a 64-bit system of 8 Z80s in line with interconnected buses and registers to run a BSD kernel. The opposite of multiplexing. What's this called? :cool:
 
MG said:
It can be done with software. Adjust the hardware to approach the same but with the existing physical circuitry if possible. It might need a memory bank for the stack of this construction.
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Sounds like a Touring Maschine implemented on Z80 emulating some 64 bit arch. Can be done, but why? Maybe turn the Z80 into some kind of bit slice processor, making registers wider but you will be stuck with byte operations on memory. An interesting project for a semester of hardware design students.
 
Crivens said:
A fools errand. No mmu, still 16 bit address bus, no caches...
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I'm not sure he's 100% serious 😄 , but it can probably be made to work if you tried hard enough (like, really hard). Would probably be pretty slow without pipelineing and superscalar architecture though, and as you say, no MMU. It's actually kind of interesting, imagine if there was some fundamental limit on what you could build in silicon, that meant you could never make anything bigger than a Z80...
 
I have at least two in my drawer in the basement. I would have more but I gave some away decades ago.
EDIT: Yep. Two in the easiest place to look. I might have a tube with a couple more elsewhere. Also found an Intel 8085A.
 
amd2900 (300 to 500 logic gates) are very old tech by now. A modern FPGA can have 100E6 to 100E9 'equivalent' logic gates so you can likely build a "proof of concept" 64 bit Z80x64 but it will be slow. Contrast with Athlon64 (~100E6 transistors), Ryzen9 (~16E9 transistors).
 
blackbird9 said:
I'm not sure he's 100% serious 😄 , but it can probably be made to work if you tried hard enough (like, really hard). Would probably be pretty slow without pipelineing and superscalar architecture though, and as you say, no MMU.
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I like the idea of just adding more Z80s to be a MMU and etc; how many Z80s would it take to run Crysis? 😆
 
In case anyone is wondering, the schematic shows a Z80 set up in a "free run". The data on the databus is $00, which is a NOP, that instruction doesn't do anything besides using clock cycles. PC (program counter) will then just increase, reading the next byte. The LEDs attached to the address bus will count up indefinitely.
 
bgavin said:
Hold my beer…
Wrote ASM in 6502….
And hated every bit of that archaic (lack of) register set.
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The Z80 was a nicer chip to program; having the alternate register set available, and being able to swap it with the main register set in a single instruction was very useful, amongst other tricks.

The 6502 had almost a 'RISC' design philosophy, cut down to the bare minimum, which meant it could be built from a relatively small number of transistors, compared to other microprocessors of the time, which made it very cheap to manufacture. Wikipedia says "When it was introduced, the 6502 was the least expensive microprocessor on the market by a considerable margin. It initially sold for less than one-sixth the cost of competing designs from larger companies, such as the 6800 or Intel 8080". https://en.wikipedia.org/wiki/MOS_Technology_6502

It is interesting that the team that designed the BBC micro, took some inspiration from the experience they gained with the 6502, when designing the first version of the ARM cpu, the "Acorn RISC machine".

I used to program 6502 assembly on the Oric and BBC micro, too. There was a Rodney Zaks Sybex book for the 6502, of course, as well as Leo Scanlon's book. I wish I'd kept my copies now.
 
SirDice said:
In case anyone is wondering, the schematic shows a Z80 set up in a "free run". The data on the databus is $00, which is a NOP, that instruction doesn't do anything besides using clock cycles. PC (program counter) will then just increase, reading the next byte. The LEDs attached to the address bus will count up indefinitely.
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Another point to note in that schematic is that they are clocking the Z80 using the 4093 cmos oscillator at only 28 Hz, according to the writing next to the CLK input (I will take their word for it). The 4093 is a quad NAND schmitt trigger, they have used one of the gates to form the oscillator shown in the circuit diagram; it appears to be using the astable multivibrator circuit shown in Fig 18 on page 4 of the 4093 datasheet https://www.ti.com/lit/ds/symlink/cd4093b.pdf?ts=1784616323201 . Of course using a schmitt trigger means the square wave will have nice sharp edges.

Each NOP instruction takes 4 t-states to execute, so the cpu in this circuit will actually execute NOP's at a rate of 7 Hz, or 7 NOP instructions per second. The data bus lines are all pulled down to logic 0 by the pulldown resistors, so the opcode is always read as 0x00, which is the opcode for the NOP instruction. So you will get to see the LEDs wired to the low address lines flashing since the chip is being clocked really, really slowly. In fact the address lines effectively work as a binary divider of a 7Hz square wave; A0 will flash at 7Hz (so, visually it will probably appear to be solid on, although if you wave your hand in front of it you may see a strobe effect), A1 will flash at 3.5 Hz, and A2 will flash at 1.75 Hz. This is possible because the memory cells that make up the chip's registers are static RAM, in fact you can single-step this chip and stop it indefinitely and it will retain the contents of its registers (although if there was external DRAM it would need to be refreshed).
 
blackbird9 said:
This is possible because the memory cells that make up the chip's registers are static RAM, in fact you can single-step this chip and stop it indefinitely and it will retain the contents of its registers
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Works on a 'modern' 6502 too (W65C02).
 
Ok, just to be fair to 6502 fans, here's a 100 MHz 6502, implmented on an FPGA: so 6502 is not dead either. https://www.e-basteln.de/computing/65f02/65f02/
And unlike the Z80 which is out of production, you can still buy a modern version of the 6502: https://www.mouser.co.uk/new/western-design-center/wdc-w65c02s/

You can buy s rPi type SBC based on the 6502 here: https://thepihut.com/products/olimex-neo6502

And, we can't forget this classic site either: http://visual6502.org/
 
blackbird9 said:
Ok, just to be fair to 6502 fans, here's a 100 MHz 6502, implmented on an FPGA: so 6502 is not dead either.
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Don't know if it's true or not, can't find the article anymore, but they took apart some bus controller from a modern PC and it had a 6502 embedded in it, running on some insane frequency. It was used as the state machine for the bus signalling/arbitration. Makes sense, it's only a few thousand transistors, it hardly makes a dent in the overal transistor count. And it's programmable, so you could update the firmware to fix bugs or add functionality once the chip has been baked.
 
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