What determines FreeBSD compatibility with a mainboard's chipset/northbridge ?

I've been wanting to get an parity-checking (ECC) memory-compatible mainboard to get the most out of ZFS's integrity-preserving design [1] for use on a home file server. I started by looking at well-known manufacturer Supermicro. It seems have the choice of several Intel northbridges, and even a couple ones made for AMD CPUs. [2]

Is there a reason to think some of them might work less reliably than others, or that some might show quirky, or plain-unsupported behavior ?

Is it possible to say if one would be on a safer side buying a 3-to-5 year old chipset (expecting better driver support in FreeBSD, but at the cost of performance), or have some recent chipsets better developer attention, that has resulted in those becoming the safer purchase ?


Chipsets themselves aren't mentionned in the Handbook's Hardware Notes ; could it be that they don't pose any driver development challenge of their own, and that compatibility and performance boil down exclusively to supporting the leaf devices attached to a southbridge, (disk controllers, NICs...) ?


[1] http://mail.opensolaris.org/pipermail/zfs-discuss/2012-January/050812.html
[2] These chipsets are: Intel C602 / C606 (socket R/LGA 2011, Intel X58 Express (socket 1366), Intel 3420 (socket 1156), Intel C214, C204, C202 (socket 1155), AMD SP5100 (Opteron 6000/4000 series), nVidia MCP55 (Opteron 1000 series)
 
I'm using two Intel 3420 boards of that manufacturer (X8SIL-F, X8SI6-F) without any problems, I think the support of leaf devices is a much greater concern (for instance, the driver for the SAS controller on the X8SI6-F board is only present in the latest FreeBSD 8.* and 9.* releases, and is still being improved upon).
You see with those 'chipset driver' bundles on Windows that they're also really just a collection of SATA, NIC, etc. drivers.

However, I'm not sure how much kernel code actually deals with the chipset itself... things like ECC are generally handled transparently by the CPU memory controller anyway, with some MCE functionality whenever the OS should be notified of some event.
 
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