Hi Everyone,
I have been investigating shared TLB Mode for the XLR Processor. I have fixed some issues that now allow me to boot the system up.
However, I sometimes face random panics/traps. The major Errors that I see are as under:
3. Trying to enter an entry in the map that already exists (Through vm_map_insert).
All of these errors look like the TLB Exception Handlers were unable to find an entry in the Page Table for a particular Virtual Address and the unresolved entry had to be moved to higher level fault routines. For entries marked with no-fault, we should always have them in the page table. However, they were not served through the TLB Miss handler and vm_fault had to be invoked. That panicked
Please let me know if you have any intuition about what could be wrong. Again, I see these errors for random addresses. Let me know if you have more questions.
Any help will be appreciated.
Cheers,
Chitrak
I have been investigating shared TLB Mode for the XLR Processor. I have fixed some issues that now allow me to boot the system up.
However, I sometimes face random panics/traps. The major Errors that I see are as under:
Code:
1. panic: vm_fault: fault on nofault entry, addr: c4f40000
cpuid = 0
KDB: stack backtrace:
0x40446c28+0x2dc (66c,40513694,4063b06c,404fb000) ra 40446fa8 sz 64
0x40446f7c+0x2c (66c,40513694,4063b06c,404fb000) ra 40448fc0 sz 32
0x40448e98+0x128 (66c,40513694,4063b06c,404fb000) ra 4044b568 sz 48
0x4044ac10+0x958 (66c,40513694,77ffdec0,404fb000) ra 40446760 sz 384
VA 0x4043675c: not in user area or heuristics failed
.text+0xc0346688 (66c,40513694,77ffdec0,404fb000) ra 0 sz 0
pid 128, process: uname
Code:
2. Mips_HitSyncDCache+0x4c (405c1000,1f,1000,c095a4b0) ra 804141a8 sz 0
smp_init_secondary+0x304 (405c1000,1f,1000,c095a4b0) ra 1000 sz 32
PC 0x1000: not in kernel
0x0+0x1000 (405c1000,1f,1000,c095a4b0) ra 0 sz 0
pid 142, process: mspsmd
cpu:1
Trap cause = 2 (TLB miss (load or instr. fetch) - kernel mode)
badvaddr = 0x405c1000, pc = 0x805a68bc, ra = 0x804141a8, sr = 0x5080dc03
[thread pid 142 tid 100059 ]
Stopped at Mips_HitSyncDCache+0x4c: cache s5,a0,0All of these errors look like the TLB Exception Handlers were unable to find an entry in the Page Table for a particular Virtual Address and the unresolved entry had to be moved to higher level fault routines. For entries marked with no-fault, we should always have them in the page table. However, they were not served through the TLB Miss handler and vm_fault had to be invoked. That panicked
Please let me know if you have any intuition about what could be wrong. Again, I see these errors for random addresses. Let me know if you have more questions.
Any help will be appreciated.
Cheers,
Chitrak