Intel Apollo Lake eMMC controller access timeout

E

Ekko

Dears,

I'm attempting to install FreeBSD 11.1 to check eMMC 5.0 compatibility via Intel SoC.
And I test it on different eMMC vendor

123.JPG


Information from git log
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commit 398d5fc6afb7ce20f0cf9ecc4fe286e72afdbf29
Author: marius <marius@FreeBSD.org>
Date: Sun Jul 23 16:11:47 2017 +0000

Support HS200/HS400

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commit e16f2fe291be05d4f487c720d571ff293ab73d10
Author: marius <marius@FreeBSD.org>
Date: Sun May 14 21:33:01 2017 +0000

Probe APL SDHCI controller
05c82724-dbea-46d9-808c-17d4d4cf35d4


dmesg:
Code: 
Copyright (c) 1992-2017 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
    The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 11.1-RELEASE #0 r321309: Fri Jul 21 02:08:28 UTC 2017
    root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64
FreeBSD clang version 4.0.0 (tags/RELEASE_400/final 297347) (based on LLVM 4.0.0)
VT(vga): resolution 640x480

sdhci_pci0: <Intel Apollo Lake eMMC 5.0 Controller> mem 0x92416000-0x92416fff,0x92415000-0x92415fff irq 39 at device 28.0 on pci0
sdhci_pci0: 1 slot(s) allocated
mmc0: <MMC/SD bus> on sdhci_pci0
isab0: <PCI-ISA bridge> at device 31.0 on pci0
isa0: <ISA bus> on isab0
acpi_button0: <Power Button> on acpi0
acpi_tz0: <Thermal Zone> on acpi0
ppc0: cannot reserve I/O port range
est0: <Enhanced SpeedStep Frequency Control> on cpu0
est1: <Enhanced SpeedStep Frequency Control> on cpu1
Timecounters tick every 1.000 msec
nvme cam probe device init
ugen0.1: <0x8086 XHCI root HUB> at usbus0
uhub0: <0x8086 XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus0
ada0 at ahcich0 bus 0 scbus0 target 0 lun 0
ada0: <WDC WD1600BEVT-22A23T0 01.01A01> ATA8-ACS SATA 2.x device
ada0: Serial Number WD-WXF0AB9L8967
ada0: 300.000MB/s transfers (SATA 2.x, UDMA6, PIO 8192bytes)
ada0: Command Queueing enabled
ada0: 152627MB (312581808 512 byte sectors)
uhub0: 15 ports with 15 removable, self powered
sdhci_pci0-slot0:  Controller timeout
sdhci_pci0-slot0: ============== REGISTER DUMP ==============
sdhci_pci0-slot0: Sys addr: 0x00000000 | Version:  0x00001002
sdhci_pci0-slot0: Blk size: 0x00000000 | Blk cnt:  0x00000000
sdhci_pci0-slot0: Argument: 0x00000000 | Trn mode: 0x00000000
sdhci_pci0-slot0: Present:  0x1fff0000 | Host ctl: 0x00000001
sdhci_pci0-slot0: Power:    0x0000000b | Blk gap:  0x00000080
sdhci_pci0-slot0: Wake-up:  0x00000000 | Clock:    0x0000fa07
sdhci_pci0-slot0: Timeout:  0x00000000 | Int stat: 0x00000001
sdhci_pci0-slot0: Int enab: 0x01ff00fb | Sig enab: 0x01ff00fb
sdhci_pci0-slot0: AC12 err: 0x00000000 | Host ctl2: 0x00000000
sdhci_pci0-slot0: Caps:     0x546ec881 | Caps2:    0x80000807
sdhci_pci0-slot0: Max curr: 0x00000000 | ADMA err: 0x00000000
sdhci_pci0-slot0: ADMA addr: 0x00000000 | Slot int: 0x00000001
sdhci_pci0-slot0: ===========================================
sdhci_pci0-slot0:  Controller timeout
sdhci_pci0-slot0: ============== REGISTER DUMP ==============
sdhci_pci0-slot0: Sys addr: 0x00000000 | Version:  0x00001002
sdhci_pci0-slot0: Blk size: 0x00000000 | Blk cnt:  0x00000000
sdhci_pci0-slot0: Argument: 0x00000000 | Trn mode: 0x00000000
sdhci_pci0-slot0: Present:  0x1fff0000 | Host ctl: 0x00000001
sdhci_pci0-slot0: Power:    0x0000000b | Blk gap:  0x00000080
sdhci_pci0-slot0: Wake-up:  0x00000000 | Clock:    0x0000fa07
sdhci_pci0-slot0: Timeout:  0x00000000 | Int stat: 0x00000001
sdhci_pci0-slot0: Int enab: 0x01ff00fb | Sig enab: 0x01ff00fb
sdhci_pci0-slot0: AC12 err: 0x00000000 | Host ctl2: 0x00000000
sdhci_pci0-slot0: Caps:     0x546ec881 | Caps2:    0x80000807
sdhci_pci0-slot0: Max curr: 0x00000000 | ADMA err: 0x00000000
sdhci_pci0-slot0: ADMA addr: 0x00000000 | Slot int: 0x00000001
sdhci_pci0-slot0: ===========================================
 
Hi all,

I have downloaded newest 10.4 and try to fix it, but there is still the problem.

FreeBSD 10.4-RELEASE Announcement
10.4-RELEASE is the first FreeBSD release to feature full support for eMMC storage, including eMMC partitions, TRIM and bus speed modes up to HS400. Please note, though, that availability of especially the DDR52, HS200 and HS400 modes requires support in the actual sdhci(4) front-end as well as by the hardware used. Also note, that the SDHCI controller part of Intel® Apollo Lake chipsets is affected by several severe silicon bugs. Apparently, it depends on the particular Apollo Lake platform whether the workarounds in place so far are sufficient to avoid timeouts on attaching sdhci(4) there.
 
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