Other Pattern rules for both .c and .S files in BSD make

[lolzdev]

I'm trying to create a Makefile for my hobby OS, I want to have rules to build object files for both .c and .S (assembly) sources.
I did it like this:

%.o: %.c
    ${CC} ${CFLAGS} -c $@ -o $<

%.o: %.S
    ${CC} ${ASFLAGS} -c $@ -o $<

as I usually do with gmake, but I get this error:
make: "/home/lorenzo/src/hydra/Makefile" line 14: warning: duplicate script for target "%.o" ignored
make: "Makefile" line 11: warning: using previous script for "%.o" defined here
what does this mean? How can I solve this issue?

 

[kpedersen]

Pattern rules aren't supported by BSD's (more POSIX'ly correct) make. However you can certainly install gmake from ports.

With BSD make, what you might want to look at instead is suffix rules. Distilled as:

OBJ= \
  main.o \
  other.o

.SUFFIXES: .c .o

prog: ${OBJ}
    ${CC} -o$@ ${OBJ}

.c.o:
    ${CC} -c $<

Also, in your pattern rules example:

    ${CC} ${ASFLAGS} -c $@ -o $<

I am fairly sure you have the $@ and $< the wrong way round. $< is the dependency to be compiled (i.e main.c). $@ is the rule artifact to satisfy (i.e prog.bin)

${CC} ${ASFLAGS} -c -o$@ $<

 

[lolzdev]

Pattern rules aren't supported by BSD's (more POSIX'ly correct) make. However you can certainly install gmake from ports.

With BSD make, what you might want to look at instead is suffix rules. Distilled as:

OBJ= \
  main.o \
  other.o

.SUFFIXES: .c .o

prog: ${OBJ}
    ${CC} -o$@ ${OBJ}

.c.o:
    ${CC} -c $<

Also, in your pattern rules example:


I am fairly sure you have the $@ and $< the wrong way round. $< is the dependency to be compiled (i.e main.c). $@ is the rule artifact to satisfy (i.e prog.bin)

${CC} ${ASFLAGS} -c -o$@ $<

Thank you! didn't know about suffix rules